As semiconductor technologies evolve, some conventional approaches for forming quarter (0.25) micron and smaller features become more problematic. One such example is local oxidation of silicon (LOCOS) for forming field oxide regions in an array of memory integrated circuit cells. In LOCOS, a nitride hard mask is patterned to cover designated active areas on a silicon substrate. During LOCOS oxidation of exposed field regions of the silicon substrate, the nitride hard mask deflects upwardly at the interface of field regions and active areas owing to encroachment of the LOCOS under the mask (i.e., encroachment into the active areas). Additionally, LOCOS formation is inherently nonplanar, which makes it relatively difficult for use in 0.25 micron or smaller geometries in large-scale integration for isolating one device from another.
Consequently, shallow-trench isolation (STI) has been suggested as a practical alternative to LOCOS for 0.25 micron and smaller topographies. With STI, a more planar structure may be achieved, especially when compared with semi-recessed LOCOS. For example, an STI structure may be planarized by subsequent etch back or chemical-mechanical polishing (CMP) to form an optimally planar surface.
A problem with STI is that a recess in an STI field oxide near an active area edge causes sub-threshold voltage conduction (leakage current) across a metal-oxide-semiconductor-field-effect-transistor (MOSFET) adjacent to a defective STI structure. It is believed that the field oxide recess causes field crowding at the active area edge of the trench leading to sub-threshold conduction. Such a recess may be caused by over polishing during CMP or deglazing.
To address this problem, others have suggested that a gate oxide be grown prior to forming an STI trench. The formed trench is then filled with an oxide. A CMP step is employed to form a surface of the field oxide planar to the deposited gate oxide (i.e., above the silicon wafer surface). Accordingly, this process avoids a field oxide recess near a gate edge and a field edge of an adjacent transistor. However, this process necessitates forming a gate oxide early, which is then subjected to subsequent processing steps which may adversely impact the quality or the integrity of the gate oxide.
Accordingly, it would be desirable to provide an STI structure that provides less probability of leakage current. Moreover, it would be desirable to provide a process which reduces probability of subthreshold voltage transistor leakage, but which also allows for gate formation later in the process.